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1 ? fn8166.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copy right intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. x9251 single supply/low powe r/256-tap/spi bus quad digitally-controlled (xdcp?) potentiometer features ? four potentiometers in one package ? 256 resistor taps?0.4% resolution ? spi serial interface for write, read, and transfer operations of the potentiometer ? wiper resistance: 100 ? typical @ v cc = 5v ? 4 non-volatile data registers for each potentiometer ? non-volatile storage of multiple wiper positions ? standby current < 5a max ?v cc : 2.7v to 5.5v operation ?50k ? , 100k ? versions of total resistance ? 100 yr. data retention ? single supply version of x9250 ? endurance: 100,000 data changes per bit per register ? 24 ld soic, 24 ld tssop ? low power cmos ? pb-free plus anneal available (rohs compliant) description the x9251 integrates four digitally controlled potentio- meters (xdcp) on a monolithic cmos integrated circuit. the digitally controlled potentiometers are imple- mented with a combination of resistor elements and cmos switches. the position of the wipers are controlled by the user through the spi bus interface. each potentiometer has associated with it a volatile wiper counter register (wcr) and four non-volatile data registers that can be di rectly written to and read by the user. the content of the wcr controls the position of the wiper. at power-up, the device recalls the content of the default data registers of each dcp (dr00, dr10, dr20, and dr30) to the corresponding wcr. the xdcp can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. functional diagram power up, interface control and v cc v ss spi r h0 r l0 dcp0 r w0 a1 so si cs hold sck wp wcr0 dr00 dr01 dr02 dr03 r h1 r l1 dcp1 r w1 wcr1 dr10 dr11 dr12 dr13 r h2 r l2 dcp2 r w2 wcr2 dr20 dr21 dr22 dr23 r h3 r l3 dcp3 r w3 wcr3 dr30 dr31 dr32 dr33 a0 interface status data sheet september 14, 2005
2 fn8166.2 september 14, 2005 ordering information part number part marking v cc limits (v) potentiomenter organization (k ? ) temp range (c) package x9251up24i x9251up i 5 10% 50 -40 to +85 24 ld pdip x9251us24* x9251us 0 to 70 24 ld soic (300mil) x9251us24z* (note) x9251us z 0 to 70 24 ld soic (300mil) (pb-free) x9251us24i* x9251us i -40 to +85 24 ld soic (300mil) x9251us24iz* (note) x9251us z i -40 to +85 24 ld soic (300mil) (pb-free) x9251uv24 x9251uv 0 to 70 24 ld tssop (4.4mm) x9251uv24z (note) x9251uv z 0 to 70 24 ld tssop (4.4mm) (pb-free) x9251uv24i x9251uv i -40 to +85 24 ld tssop (4.4mm) x9251uv24iz (note) x9251uv z i -40 to +85 24 ld tssop (4.4mm) (pb-free) x9251tp24i 100 -40 to +85 24 ld pdip x9251ts24* x9251ts 0 to 70 24 ld soic (300mil) x9251ts24z* (note) x9251ts z 0 to 70 24 ld soic (300mil) (pb-free) x9251ts24i* x9251ts i -40 to +85 24 ld soic (300mil) x9251ts24iz* (note) x9251ts z i -40 to +85 24 ld soic (300mil) (pb-free) x9251tv24 x9251tv 0 to 70 24 ld tssop (4.4mm) x9251tv24z (note) x9251tv z 0 to 70 24 ld tssop (4.4mm) (pb-free) x9251tv24i x9251tv i -40 to +85 24 ld tssop (4.4mm) x9251tv24iz (note) x9251tv z i -40 to +85 24 ld tssop (4.4mm) (pb-free) x9251us24-2.7* x9251us f 2.7 to 5.5 50 0 to 70 24 ld soic (300mil) x9251us24z-2.7* (note) x9251us z f 0 to 70 24 ld soic (300mil) (pb-free) x9251us24i-2.7* x9251us g -40 to +85 24 ld soic (300mil) x9251us24iz-2.7* (note) x9251us z g -40 to +85 24 ld soic (300mil) (pb-free) x9251uv24-2.7 x9251uv f 0 to 70 24 ld tssop (4.4mm) x9251uv24z-2.7 (note) x9251uv z f 0 to 70 24 ld tssop (4.4mm) (pb-free) x9251uv24i-2.7 x9251uv g -40 to +85 24 ld tssop (4.4mm) x9251uv24iz-2.7 (note) x9251uv z g -40 to +85 24 ld tssop (4.4mm) (pb-free) x9251ts24-2.7* x9251ts f 100 0 to 70 24 ld soic (300mil) x9251ts24z-2.7* (note) x9251ts z f 0 to 70 24 ld soic (300mil) (pb-free) x9251ts24i-2.7* x9251ts g -40 to +85 24 ld soic (300mil) x9251ts24iz-2.7* (note) x9251ts z g -40 to +85 24 ld soic (300mil) (pb-free) x9251tv24-2.7 x9251tv f 0 to 70 24 ld tssop (4.4mm) x9251tv24z-2.7 (note) x9251tv z f 0 to 70 24 ld tssop (4.4mm) (pb-free) x9251tv24i-2.7 x9251tv g -40 to +85 24 ld tssop (4.4mm) x9251tv24iz-2.7 (note) x9251tv z g -40 to +85 24 ld tssop (4.4mm) (pb-free) *add "t1" suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. x9251
3 fn8166.2 september 14, 2005 circuit level applications ? vary the gain of a voltage amplifier ? provide programmable dc reference voltages for comparators and detectors ? control the volume in audio circuits ? trim out the offset voltage error in a voltage ampli- fier circuit ? set the output voltage of a voltage regulator ? trim the resistance in wheatstone bridge circuits ? control the gain, characteristic frequency and q-factor in filter circuits ? set the scale factor and zero point in sensor signal conditioning circuits ? vary the frequency and duty cycle of timer ics ? vary the dc biasing of a pin diode attenuator in rf circuits ? provide a control variable (i, v, or r) in feedback circuits system level applications ? adjust the contrast in lcd displays ? control the power level of led transmitters in communication systems ? set and regulate the dc biasing point in an rf power amplifier in wireless systems ? control the gain in audio and home entertainment systems ? provide the variable dc bi as for tuners in rf wire- less systems ? set the operating points in temperature control systems ? control the operating point for sensors in industrial systems ? trim offset and gain errors in artificial intelligent systems pin configuration pin assignments note 1: a0 - a1 device address pins must be tied to a logic level. pin (soic) symbol function 1 so serial data output for spi bus 2 a0 device address for spi bus. (see note 1) 3r w3 wiper terminal of dcp3 4r h3 high terminal of dcp3 5r l3 low terminal of dcp3 7v cc system supply voltage 8r l0 low terminal of dcp0 9r h0 high terminal of dcp0 10 r w0 wiper terminal of dcp0 11 cs spi bus. chip select active low input 12 wp hardware write protect - active low 13 si serial data input for spi bus 14 a1 device address for spi bus. (see note 1) 15 r l1 low terminal of dcp1 16 r h1 high terminal of dcp1 17 r w1 wiper terminal of dcp1 18 v ss system ground 20 r w2 wiper terminal of dcp2 21 r h2 high terminal of dcp2 22 r l2 low terminal of dcp2 23 sck serial clock for spi bus 24 hold device select. pauses the spi serial bus. 6, 19 nc no connect so a0 r w3 nc v cc r l0 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 hold sck r l2 r h2 r w2 nc v ss r w1 r h1 r l1 soic/tssop x9251 r h3 14 13 11 12 r l3 r h0 r w0 cs a1 si wp x9251
4 fn8166.2 september 14, 2005 pin descriptions bus interface pins s erial o utput (so) so is a serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. s erial i nput (si) si is the serial data input pin. all opcodes, byte addresses and data to be written to the device registers are input on this pin. data is latched by the rising edge of the serial clock. s erial c lock (sck) the sck input is used to clock data into and out of the x9251. h old (hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sc k is low. to resume communication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. d evice a ddress (a1 - a0) the address inputs are used to set the two least significant bits of the slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the x9251. device pins a1 - a0 must be tie to a logic level which specify the internal address of the device, see figures 2, 3, 4, 5 and 6. c hip s elect (cs ) when cs is high, the x9251 is deselected and the so pin is at high impedance, and (unless an internal write cycle is underway) the device is in the standby state. cs low enables the x9251, placing it in the active power mode. it should be noted that after a power-up, a high to low transition on cs is required prior to the start of any operation. potentiometer pins r h , r l the r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. since there are 4 potentiometers, there are 4 sets of r h and r l such that r h0 and r l0 are the terminals of dcp0 and so on. r w the wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. since there are 4 potentiometers, there are 4 sets of r w such that r w0 is the terminals of dcp0 and so on. supply pins s ystem s upply v oltage (v cc ) and s upply g round (v ss ) the v cc pin is the system supply voltage. the v ss pin is the system ground. other pins n o c onnect no connect pins should be left floating. this pins are used for intersil manufacturing and testing purposes. h ardware w rite p rotect i nput (wp ) the wp pin when low prevents non-volatile writes to the data registers. principles of operation the x9251 is an integrated circuit incorporating four dcps and their associated registers and counters, and a serial interface providing direct communication between a host and the potentiometers. dcp description each dcp is implemented with a combination of resistor elements and cmos switches. the physical ends of each dcp are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l pins). the rw pin is an intermediate node, equivalent to the wiper terminal of a mechanical potentiometer. the position of the wiper terminal within the dcp is controlled by an 8-bit volatile wiper counter register (wcr). x9251
5 fn8166.2 september 14, 2005 figure 1. detailed potentiometer block diagram power up and down recommendations. there are no restrictions on the power-up or power- down conditions of v cc and the voltages applied to the potentiometer pins provided that v cc is always more positive than or equal to v h , v l , and v w , i.e., v cc v h , v l , v w . the v cc ramp rate specification is always in effect. wiper counter register (wcr) the x9251 contains four wiper counter registers, one for each potentiometer. the wiper counter register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 wiper positions along its resistor array. the contents of the wcr can be altered in four ways: it may be written directly by the host via the write wiper counter register in struction (serial load); it may be written indirectly by transfer ring the contents of one of four associated data registers via the xfr data register instruction (paralle l load); it can be modified one step at a time by the increment/decrement instruction (see instructio n section for more details). finally, it is loaded with the contents of its data register zero (dr#0) upon power-up. (see figure 1.) the wiper counter register is a volatile register; that is, its contents are lost when the x9251 is powered-down. although the register is automatically loaded with the value in dr#0 upon power-up, this may be different from the value present at power-down. power-up guidelines are recommended to ensure proper loadings of the dr#0 value into the wcr#. data registers (dr) each of the four dcps has four 8-bit non-volatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the associated wiper counter register. all operations changing data in one of the data registers is a non-volatile operation and takes a maximum of 10ms. if the application does not require storage of multiple settings for the potentiomete r, the data registers can be used as regular memory locations for system parameters or user preference data. bits [7:0] are used to store one of the 256 wiper positions or data (0~255). status register (sr) this 1-bit status register is used to store the system status. wip: write in progress status bit, read only. ? when wip=1, indicates that high-voltage write cycle is in progress. ? when wip=0, indicates that no high-voltage write cycle is in progress. serial data path from interface circuitry dr#0 serial bus input parallel bus input counter register inc/dec logic up/dn clk modified sck up/dn 8 8 counter if wcr = 00[h] then r w is closet to r l if wcr = ff[h] then r w is closet to r h wiper (wcr#) #: 0, 1, 2, or 3 one of four potentiometers dr#2 dr#1 dr#3 - - - decode dcp core r w r h r l x9251
6 fn8166.2 september 14, 2005 table 1. wiper counter register, wcr (8-bit), wcr[7:0]: used to store the current wiper position (volatile). table 2. data register, dr (8-bit), dr[7:0]: used to store wiper positions or data (non-volatile). serial interface the x9251 supports the spi interface hardware conventions. the device is accessed via the si input with data clocked in, on the rising sck. cs must be low and the hold and wp pins must be high during the entire operation. the so and si pins can be connected together, since they have three state outputs. this can help to reduce system pin count. i dentification b yte the first byte sent to the x9251 from the host, following a cs going high to low, is called the identification byte. the most significant four bits of the identification byte are a device type identifier, id[3:0]. for the x9251, this is fixed as 0101 (refer to table 3). the least significant four bits of the identification byte are the slave address bits, ad[3:0]. for the x9251, a3 is 0, a2 is 0, a1 is the logic value at the input pin a1, and a0 is the logic value at the input pin a0. only the device which slave address matches the incoming bits sent by the master executes the instruction. the a1 and a0 inputs can be actively driven by cmos input signals or tied to v cc or v ss . i nstruction b yte the next byte sent to the x9251 contains the instruction and register pointer information. the four most significant bits are used provide the instruction opcode (i[3:0]). the rb and ra bits point to one of the four data registers of each associated xdcp. the least two significant bits point to one of four wiper counter registers or dcps.the format is shown below in table 4. table 3. identification byte format table 4. instruction byte format wcr7 wcr6 wcr5 wcr4 wcr3 wcr2 wcr1 wcr0 (msb) (lsb) bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 (msb) (lsb) id3 id2 id1 id0 a3 a2 a1 a0 010100pin a1 logic value pin a0 logic value (msb) (lsb) device type identifier slave address i3 i2 i1 i0 rb ra p1 p0 (msb) (lsb) instruction register dcp selection opcode selection (wcr selection) x9251
7 fn8166.2 september 14, 2005 data register selection #: 0, 1, 2, or 3 table 5. instruction set note: 1/0 = data is one or zero register rb ra dr#0 0 0 dr#1 0 1 dr#2 1 0 dr#3 1 1 instruction instruction set operation i3 i2 i1 i0 rb ra p1 p0 read wiper counter register 1 0 0 1 0 0 1/0 1/0 read the contents of the wiper counter register pointed to by p1 - p0 write wiper counter register 1 0 1 0 0 0 1/0 1/0 write new value to the wiper counter register pointed to by p1 - p0 read data register 1 0 1 1 1/0 1/0 1/0 1/0 read the contents of the data register pointed to by p1 - p0 and rb - ra write data register 1 1 0 0 1/0 1/0 1/0 1/0 write new value to the data register pointed to by p1 - p0 and rb - ra xfr data register to wiper counter register 1 1 0 1 1/0 1/0 1/0 1/0 transfer the contents of the data register pointed to by p1 - p0 and rb - ra to its associated wiper counter register xfr wiper counter register to data register 1 1 1 0 1/0 1/0 1/0 1/0 transfer the contents of the wiper counter register pointed to by p1 - p0 to the data register pointed to by rb - ra global xfr data registers to wiper counter registers 0 0 0 1 1/0 1/0 0 0 transfer the contents of the data registers pointed to by rb - ra of all four pots to their respective wiper counter registers global xfr wiper counter registers to data register 1 0 0 0 1/0 1/0 0 0 transfer the contents of both wiper counter registers to their respective data registers pointed to by rb - ra of all four pots increment/decrement wiper counter register 0 0 1 0 0 0 1/0 1/0 enable increment/decrement of the control latch pointed to by p1 - p0 x9251
8 fn8166.2 september 14, 2005 instructions four of the nine instructions are three bytes in length. these instructions are: ? read wiper counter register ? read the current wiper position of the selected potentiometer, ? write wiper counter register ? change current wiper position of the selected potentiometer, ? read data register ? read the contents of the selected data register, ? write data register ? write a new value to the selected data register, ? read status ? this command returns the contents of the wip bit which indica tes if the internal write cycle is in progress. the basic sequence of the th ree byte instructions is illustrated in figure 3. th ese three-byte instructions exchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a static ram, with the static ram controlling the wiper positio n. the response of the wiper to this action is delayed by t wrl . a transfer from the wcr (current wiper positio n), to a data register is a write to non-volatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four potentiometer?s wcr, and one of its associated registers, drs; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. the read status register instruction is the only unique format (see figure 5). four instructions require a two-byte sequence to complete. these instructions transfer data between the host and the x9251; ei ther between the host and one of the data registers or directly between the host and the wiper counter register. these instructions are: ? xfr data register to wiper counter register ? this transfers the contents of one specified data register to the associated wiper counter register. ? xfr wiper counter regist er to data register ? this transfers the contents of the specified wiper counter register to the specified associated data register. ? global xfr data register to wiper counter register ? this transfers the contents of all speci- fied data registers to the associated wiper counter registers. ? global xfr wiper counter register to data register ? this transfers the contents of all wiper counter registers to the specified associated data registers. increment/decrement command the final command is increment/decrement (see figures 6 and 7). the increment/decrement command is different from the other commands. once the command is issued and the x9251 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capab ility to the host. for each sck clock pulse (t high ) while si is high, the selected wiper moves one wiper position towards the r h terminal. similarly, for each sck clock pulse while si is low, the sele cted wiper moves one wiper position towards the r l terminal. a de tailed illustration of the sequence and timing for this operation are shown. see instruction format for more details. x9251
9 fn8166.2 september 14, 2005 figure 2. two-byte instruction sequence figure 3. three-byte instruction sequence spi interface; write case figure 4. three-byte instruction sequence spi interface, read case id3 id2 id1 id0 0 a1 a0 i3 i2 i1 rb ra p0 sck si cs 0101 device id internal instruction opcode address register 0 i0 p1 address dcp/wcr address 0 0 0101 a1 a0 i3 i2 i1 i0 rb ra p0 sck si d7 d6 d5 d4 d3 d2 d1 d0 cs 00 id3 id2 id1 id0 device id internal instruction opcode address register address dcp/wcr address 00 p1 data for wcr[7:0] or dr[7:0] 0101 a1 a0 i3 i2 i1 i0 rb ra p0 sck si d7 d6 d5 d4 d3 d2 d1 d0 cs 00 id3 id2 id1 id0 device id internal instruction opcode address register address dcp/wcr address 00 p1 wcr[7:0] s0 x x x xx xx x don?t care or data register bit [7:0] x9251
10 fn8166.2 september 14, 2005 figure 5. three-byte instruction sequence (read status register figure 6. increment/decrement instruction sequence figure 7. increment/decrement timing spec wip status bit 0 101 a1 a0 i3 i2 i1 i0 rb ra p0 sck si cs 00 id3 id2 id1 id0 device id internal instruction opcode address register address pot/wcr address 00 p1 0 0 0 00 00 101 1 0101 a1 a0 i3 i2 i1 i0 rb ra p0 sck si cs 00 id3 id2 id1 id0 device id internal instruction opcode address register address pot/wcr address 00 p1 i n c 1 i n c 2 i n c n d e c 1 d e c n sck si r w inc/dec cmd issued t wrid voltage out x9251
11 fn8166.2 september 14, 2005 instruction format read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) write data register (dr) global transfer data register (dr) to wiper counter register (wcr) notes: (1) ?a1 ~ a0?: stands for the device addresses sent by the master. (2) wpx refers to wiper position data in the counter register (2) ?i?: stands for the increment operation, si held high during active sck phase (high). (3) ?d?: stands for the decrement operation, si held low during active sck phase (high). cs falling edge device type identifier device addresses instruction opcode wcr addresses wiper position (sent by x9251 on so) cs rising edge 0 1 0 100a1a010010000 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 cs falling edge device type identifier device addresses instruction opcode wcr addresses data byte (sent by host on si) cs rising edge 010100a1a010100000 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses data byte (sent by x9271 on so) cs rising edge 010100a1a01011rbrap1 p0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses data byte (sent by host on si) cs rising edge high-voltage write cycle 0 10100a1a01100rbrap1 p0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 cs falling edge device type identifier device addresses instruction opcode dr addresses cs rising edge 010100a1a00001rbra00 x9251
12 fn8166.2 september 14, 2005 global transfer wiper counter register (wcr) to data register (dr) transfer wiper counter register (wcr) to data register (dr) transfer data register (dr) to wiper counter register (wcr) increment/decrement wiper counter register (wcr) read status register (sr) notes: (1) ?a1 ~ a0?: stands for the device addresses sent by the master. (2) wpx refers to wiper position data in the counter register (2) ?i?: stands for the increment operation, si held high during active sck phase (high). (3) ?d?: stands for the decrement operation, si held low during active sck phase (high). cs falling edge device type identifier device addresses instruction opcode dr addresses cs rising edge high-voltage write cycle 0 10 100a1a01000rbra00 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses cs rising edge high-voltage write cycle 01 0100a1a01110rbra0 0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses cs rising edge 0 1 0 100a1a01101rbra0 0 cs falling edge device type identifier device addresses instruction opcode wcr addresses increment/decrement (sent by master on si) cs rising edge 0 1 0 1 0 0 a1 a0 0 0 1 0 x x 0 0 i/d i/d . . . . i/d i/d cs falling edge device type identifier device addresses instruction opcode wcr addresses data byte (sent by x9251 on so) cs rising edge 0 1 0 100a1a0010100010 0 0 0 0 0 0 wip x9251
13 fn8166.2 september 14, 2005 absolute maximum ratings temperature under bias .................... -65 c to +135 c storage temperature ......................... -65 c to +150 c voltage on sck, any address input, v cc with respect to v ss ................................. -1v to +7v ? v = | (v h - vl) |................................................... 5.5v lead temperature (soldering, 10s) .................... 300 c i w (10s) ..............................................................6ma comment stresses above those liste d under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. analog characteristics (over recommended industrial operating conditions unless otherwise stated.) notes: (1) absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper positi on when used as a potentiometer. (2) relative linearity is utilized to determi ne the actual change in voltage between tw o successive tap positions when used as a potentiometer. it is a measure of the error in step size. (3) mi = rtot / 255 or (r h - r l ) / 255, single pot (4) during power up v cc > v h , v l , and v w . (5) n = 0, 1, 2, ?,255; m =0, 1, 2, ?, 254. symbol parameter limits test conditions min. typ. max. units r total end to end resistance 100 k ? t version r total end to end resistance 50 k ? u version end to end resistance tolerance 20 % power rating 50 mw 25 c, each pot i w wiper current 3 ma r w wiper resistance 300 ? i w = @ v cc = 3v 150 ? i w = @ v cc = 5v v term voltage on any r h or r l pin v ss v cc vv ss = 0v noise -120 dbv / hz ref: 1v resolution 0.4 % absolute linearity (1) -1 +1 mi (3) r w(n)(actual) - r w(n)(expected) (5) relative linearity (2) -0.6 +0.6 mi (3) r w(n + 1) - [r w(n) + mi ] (5) temperature coefficient of r total 300 ppm/ c ratiometric temp. coefficient -20 +20 ppm/c c h /c l /c w potentiometer capacitances 10/10/25 pf see macro model recommended operating conditions temp min. max. commercial 0 c+70 c industrial -40 c+85 c device supply voltage (v cc ) limits (4) x9251 5v 10% x9251-2.7 2.7v to 5.5v v(v cc ) r tota l v(v cc ) r tota l x9251
14 fn8166.2 september 14, 2005 d.c. operating characteristics (over the recommended operating condit ions unless otherwise specified.) endurance and data retention capacitance power-up timing a.c. test conditions notes: (6) this parameter is not 100% tested (7) t pur and t puw are the delays required from the time the (last) power supply (v cc -) is stable until the specif ic instruction can be issued. these parameters are periodically sampled and not 100% tested. symbol parameter limits test conditions min. typ. max. units i cc1 v cc supply current (active) 400 af sck = 2.5 mhz, so = open, v cc = 6v other inputs = v ss i cc2 v cc supply current (non-volatile write) 15maf sck = 2.5mhz, so = open, v cc = 6v other inputs = v ss i sb v cc current (standby) 3 asck = si = v ss , addr. = v ss , cs = v cc = 6v i li input leakage current 10 av in = v ss to v cc i lo output leakage current 10 av out = v ss to v cc v ih input high voltage v cc x 0.7 v cc + 1 v v il input low voltage -1 v cc x 0.3 v v ol output low voltage 0.4 v i ol = 3ma v oh output high voltage v cc - 0.8 v i oh = -1ma, v cc +3v v oh output high voltage v cc - 0.4 v i oh = -0.4ma, v cc +3v parameter min. units minimum endurance 100,000 data changes per bit per register data retention 100 years symbol test max. units test conditions c in/out (6 ) input / output capacitance (si) 8pf v out = 0v c out (6) output capacitance (so) 8pf v out = 0v c in (6) input capacitance (a0, a1, cs , wp , hold , and sck) 6pf v in = 0v symbol parameter min. max. units t r v cc (6) v cc power-up rate 0.2 50 v/ms t pur (7) power-up to initiation of read operation 1 ms t puw (7) power-up to initiation of write operation 50 ms i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 x9251
15 fn8166.2 september 14, 2005 equivalent a.c. load circuit ac timing symbol parameter min. max. units f sck spi clock frequency 2 mhz t cyc spi clock cycle rime 500 ns t wh spi clock high rime 200 ns t wl spi clock low time 200 ns t lead lead time 250 ns t lag lag time 250 ns t su si, sck, hold and cs input setup time 50 ns t h si, sck, hold and cs input hold time 50 ns t ri si, sck, hold and cs input rise time 2 s t fi si, sck, hold and cs input fall time 2 s t dis so output disable time 0 250 ns t v so output valid time 200 ns t ho so output hold time 0 ns t ro so output rise time 100 ns t fo so output fall time 100 ns t hold hold time 400 ns t hsu hold setup time 100 ns t hh hold hold time 100 ns t hz hold low to output in high z 100 ns t lz hold high to output in low z 100 ns t i noise suppression time constant at si, sck, hold and cs inputs 10 ns t cs cs deselect time 2 s t wpasu wp , a0 setup time 0 ns t wpah wp , a0 hold time 0 ns r h 10pf c l c l r w r total c w 25pf 10pf r l spice macromodel v cc 2k ? 10pf so pin 2k ? x9251
16 fn8166.2 september 14, 2005 high-voltage wr ite cycle timing xdcp timing symbol table symbol parameter typ. max. units t wr high-voltage write cycle time (store instructions) 5 10 ms symbol parameter min. max. units t wrpo wiper response time after the third (last) power supply is stable 5 10 s t wrl wiper response time after instruction issued (all load instructions) 5 10 s waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x9251
17 fn8166.2 september 14, 2005 timing diagrams input timing output timing hold timing ... cs sck si so msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck so si addr msb lsb t dis t ho t v ... ... cs sck so si hold t hsu t hh t lz t hz t hold t ro t fo x9251
18 fn8166.2 september 14, 2005 xdcp timing (for all load instructions) write protect and device address pins timing ... cs sck si msb lsb vwx t wrl ... so high impedance cs wp a0 a1 t wpasu t wpah (any instruction) x9251
19 fn8166.2 september 14, 2005 applications information basic configurations of electronic potentiometers application circuits v r rw +v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current noninverting amplifier voltage regulator offset voltage adjustment comparator with hysterisis + ? v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + ? v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) rl l = {r 1 /(r 1 +r 2 )} v o (min) 100k ? 10k ? 10k ? 10k ? -12v +12v tl072 + ? v s v o r 2 r 1 } } x9251
20 fn8166.2 september 14, 2005 application circuits (continued) attenuator filter inverting amplifier equivalent l-r circuit + ? v s v o r 3 r 1 v o = g v s -1/2 g +1/2 g o = 1 + r 2 /r 1 fc = 1/(2 rc) + ? v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + ? v s function generator r 2 r 4 r 1 = r 2 = r 3 = r 4 = 10k ? + ? v s r 2 r 1 r c } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + ? r 2 + ? r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c v o x9251
21 fn8166.2 september 14, 2005 packaging information note: all dimensions in inches (in parentheses in millimeters) 24-lead plastic, tssop, package code v24 .169 (4.3) .177 (4.5) .252 (6.4) bsc .026 (.65) bsc .303 (7.70) .311 (7.90) .002 (.06) .005 (.15) .047 (1.20) .0075 (.19) .0118 (.30) see detail ?a? .031 (.80) .041 (1.05) .010 (.25) .020 (.50) .030 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical 0 - 8 x9251
22 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8166.2 september 14, 2005 packaging information 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) pin 1 pin 1 index 0.050 (1.27) 0.598 (15.20) 0.610 (15.49) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4x) 7 24-lead plastic, soic, package code s24 note: all dimensions in inches (in parentheses in millimeters) 0.420" 0.050" typical 0.050" typical 0.030" typical 24 places footprint 0.010 (0.25) 0.020 (0.50) 0.015 (0.40) 0.050 (1.27) 0.009 (0.22) 0.013 (0.33) 0 - 8 x 45 x9251

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